Micromodeling of Analog Circuits for Hierarchical Circuit Design

Hierarchy plays a signi cant role in the design of digital and analog circuits. At each level of the hierarchy it becomes essential to evaluate if a sub-block design is feasible and if so which design style is the best candidate for the particular problem. This paper proposes a general methodology for evaluating the feasibility and the performance of sub-blocks at all levels of the hierarchy. A modi ed simplicial approximation technique is used to generate the feasibility macromodel and a layered volume-slicing methodology with radial basis functions is used to generate the performance macromodel. However, due to lack of space, only details of the performance macromodeling techniques are included. Macromodels are developed and veri ed for analog blocks at three di erent levels of hierarchy (current mirror, opamp, and A/D converter).